Firstly, it now has a name (…and logo):
From my first name and Calculator, the CPU and year. Anyway… News!
The Serial Port has been implemented, but I’m still struggling with the software for the Serial port. It doesn’t help that I’ve not had time to work seriously on it, either.
Images of the thing will appear soon.
The Memory Map is very simple, 8KB ROM at 0000H, and also up to 64KB RAM at 0000H.
Currently though, the Map is:
This is the Simple Version.
When this is finished, the Memory Map should look like this:
|Address||At Power On||CP/M Mode|
|0000H||8KB ROM||8KB RAM|
|08H||SIO/2 Channel A Data|
|09H||SIO/2 Channel B Data|
|0AH||SIO/2 Channel A Control|
|0BH||SIO/2 Channel B Control|
|0CH||CTC Channel 0 (SIO/2 Ch. A BAUD Generator)|
|0DH||CTC Channel 1 (SIO/2 Ch. B BAUD Generator)|
|0EH||CTC Channel 2|
|0FH||CTC Channel 3|